/*
 * X1830 common routines
 *
 * Copyright (c) 2017 Ingenic Semiconductor Co.,Ltd
 * Author: Zoro <ykli@ingenic.cn>
 * Based on: arch/mips/cpu/xburst/jz4775/jz4775.c
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <common.h>
#include <asm/sections.h>
#include <asm/io.h>
#include <spl.h>
#include <asm/arch/jzsoc.h>

#ifdef CONFIG_SPL_BUILD

/* Pointer to as well as the global data structure for SPL */
DECLARE_GLOBAL_DATA_PTR;
gd_t gdata __attribute__ ((section(".data")));

extern void pll_init(void);
extern void sdram_init(void);

void board_init_f(ulong dummy)
{
	void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
	unsigned int clkgr;

	/* Set global data pointer */
	gd = &gdata;

	/* Enable basic clocks */
	clkgr = ~(CPM_CLKGR0_DDR | CPM_CLKGR0_TCU | CPM_CLKGR0_SFC);
	writel(clkgr, cpm_regs + CPM_CLKGR0);
	clkgr = ~(CPM_CLKGR1_CPU | CPM_CLKGR1_APB0 | CPM_CLKGR1_OST | CPM_CLKGR1_AHB0);
	writel(clkgr, cpm_regs + CPM_CLKGR1);

	timer_init();
	pll_init();
	sdram_init();

	/* Enable UART1 clock */
	writel(readl(cpm_regs + CPM_CLKGR0) & ~CPM_CLKGR0_UART1, cpm_regs + CPM_CLKGR0);

#ifdef CONFIG_SPL_SERIAL_SUPPORT
	preloader_console_init();
#endif


	/* Clear the BSS */
	memset(__bss_start, 0, (char *)&__bss_end - __bss_start);

	board_init_r(NULL, 0);
}

extern void flush_cache_all(void);

void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
	typedef void __noreturn (*image_entry_noargs_t)(void);

	image_entry_noargs_t image_entry =
			(image_entry_noargs_t) spl_image->entry_point;

	flush_cache_all();

	debug("image entry point: 0x%lX\n", spl_image->entry_point);
	image_entry();
}

#endif /* CONFIG_SPL_BUILD */
